Resistance variable memory structure and method of forming the same

ABSTRACT

A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric.

PRIORITY CLAIM

The present application is a continuation application of U.S. patent application Ser. No. 13/896,064, filed May 16, 2013, entitled “RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME”, issuing as U.S. Pat. No. 9,312,482, which claims the benefit of U.S. Provisional Application No. 61/799,092 entitled “RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME” filed Mar. 15, 2013, herein incorporated by reference in their entireties.

TECHNICAL FIELD

This disclosure relates generally to a semiconductor structure and, more particularly, to a resistance variable memory structure and method of forming a resistance variable memory structure.

BACKGROUND

In integrated circuit (IC) devices, resistive random access memory (RRAM) is an emerging technology for next generation non-volatile memory devices. Generally, RRAM typically use a dielectric material, which although normally insulating can be made to conduct through a filament or conduction path formed after application of a specific voltage. Once the filament is formed, it may be set (i.e., re-formed, resulting in a lower resistance across the RRAM) or reset (i.e., broken, resulting in a high resistance across the RRAM) by appropriately applied voltages. The low and high resistance states can be utilized to indicate a digital signal of “1” or “0” depending upon the resistance state, and thereby provide a non-volatile memory cell that can store a bit.

From an application point of view, RRAM has many advantages. RRAM has a simple cell structure and CMOS logic comparable processes which result in a reduction of the manufacturing complexity and cost in comparison with other non-volatile memory structures. Despite the attractive properties noted above, a number of challenges exist in connection with developing RRAM. Various techniques directed at configurations and materials of these RRAMs have been implemented to try and further improve device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure may be understood from the following detailed description and the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flowchart of a method of forming a semiconductor structure having a resistance variable memory structure according to at least one embodiment of this disclosure.

FIGS. 2A to 2L are cross-sectional views of semiconductor structures having a resistance variable memory structure at various stages of manufacture according to one or more embodiments of the method of FIG. 1.

DETAILED DESCRIPTION

The making and using of illustrative embodiments are discussed in detail below. It should be appreciated, however, that the disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

According to one or more embodiments of this disclosure, the semiconductor structure having a resistance variable memory structure is formed within a chip region of a substrate. A plurality of semiconductor chip regions is marked on the substrate by scribe lines between the chip regions. The substrate will go through a variety of cleaning, layering, patterning, etching and doping steps to form the semiconductor structures. The term “substrate” herein generally refers to a bulk substrate on which various layers and device structures are formed. In some embodiments, the bulk substrate includes silicon or a compound semiconductor, such as GaAs, InP, Si/Ge, or SiC. Examples of the layers include dielectric layers, doped layers, polysilicon layers or conductive layers. Examples of the device structures include transistors, resistors, and/or capacitors, which may be interconnected through an interconnect layer to additional integrated circuits.

FIG. 1 is a flowchart of a method 100 of forming a semiconductor structure having a resistance variable memory structure according to at least one embodiment of this disclosure. FIGS. 2A to 2L are cross-sectional views of semiconductor structures (200A, 200B and 200C) having a resistance variable memory structure at various stages of manufacture according to various embodiments of the method 100 of FIG. 1. Additional processes may be provided before, during, or after the method 100 of FIG. 1. Various figures have been simplified for a better understanding of the inventive concepts of the present disclosure.

Referring now to FIG. 1, the flowchart of the method 100 begins with operation 101. A conductive structure is formed embedded in a dielectric layer. In at least one embodiment, the dielectric layer includes multiple dielectric layers formed over a substrate. At least one conductive structure is formed over the substrate and embedded in multiple dielectric layers. The method 100 continues with operation 102 in which an etching stop layer is optionally formed over the conductive structure and the dielectric layer. The method 100 continues with operation 103 in which a protection material is formed over the etching stop layer.

Referring to FIG. 2A, which is an enlarged cross-sectional view of a portion of a semiconductor structure 200A having a resistance variable memory structure after performing operations 101-103. The semiconductor structure 200A includes a substrate (not shown) such as a silicon carbide (SiC) substrate, GaAs, InP, Si/Ge or a silicon substrate. In some embodiments, the substrate includes a plurality of layers formed over a top surface of the substrate. Examples of the layers include dielectric layers, doped layers, polysilicon layers or conductive layers. The substrate further includes a plurality of device structures formed within the plurality of layers. Examples of the device structures include transistors, resistors, and/or capacitors.

In the illustrated examples of FIGS. 2A-2H, the semiconductor structures 200A include a dielectric layer 203 formed over a top surface of the substrate (not shown) in a memory region 201 and a periphery region 202. The dielectric layer 203 comprise silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, tetra-ethyl-ortho-silicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, low-k dielectric material, or combinations thereof. The formation process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD) or spin-on glass (SOG).

A conductive structure 205 is formed embedded in the dielectric layer 203 in each memory region 201 and periphery region 202. In certain embodiments, the conductive structure 205 includes a conductive interconnect, a doped region or a silicide region. In some embodiments, the conductive structure 205 includes Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, silicon or combinations thereof. In the illustrated example of FIG. 2A, the semiconductor structure 200A may be formed by lithography patterning and etching in the dielectric layer 203. A metal layer deposition and planarization processes are performed over the dielectric layers 203 to form the conductive structure 205. A top surface of the conductive structure 205 is substantially coplanar with a top surface the dielectric layer 203.

An etching stop layer 207 is optionally formed over the conductive structure 205 and the dielectric layer 203 in the memory region 201 and the periphery region 202. The etching stop layer 207 halts an etching process from proceeding further down into the dielectric layers 203 and the conductive structure 205 during a formation stage for a second electrode shown in FIG. 2G. The etching stop layer 207 formed over the top surface of the conductive structure 205 prevents the conductive structure 205 from being oxidized. Also, the etching stop layer 207 formed over the top surface of the conductive structure 205 prevents the substance in the conductive structure 205 from diffusing out to contaminate other layers during the formation stage for the second electrode shown in FIG. 2G. In certain embodiments, the etching stop layer 207 includes a dielectric material such as silicon carbide or silicon oxy-nitride. The formation process may include chemical vapor deposition (CVD), atomic layer deposition (ALD) or plasma enhanced CVD (PECVD).

A protection material 209 is formed over the conductive structure 205 and the dielectric layer 203, and over the etching stop layer 207 (if the etching stop layer 207 exists). The protection material 209 includes a substantially oxygen-free dielectric material. In certain embodiments, the protection material 209 includes silicon nitride. The protection material 209 may protect conductive paths between the following formed first electrode and second electrode and enhance the electrical characteristic stability for the resistance variable memory structure. A further explanation would be described below.

Referring back to FIG. 1, method 100 continues with operation 104. In operation 104, an opening is formed in the protection material and the etching stop layer to expose a portion of the conductive structure. The opening has a sidewall surface.

Referring to FIG. 2B, which is a cross-sectional view of a portion of the semiconductor structure 200A after performing operation 104. In the memory region 201, an opening 211 is etched in the protection material 209 (also the etching stop layer 207) to expose a portion of the conductive structure 205. The opening 211 has an interior sidewall surface 211A. The opening 211 is formed by suitable process, including lithography patterning, and etching processes.

Referring back to FIG. 1, method 100 continues with operation 105. In operation 105, the opening is partially filled with a first electrode material over the conductive structure to form a first electrode. In at least one embodiment, the opening is filled with the first electrode material to less than a top surface of the dielectric layer. The first electrode has a top surface and a first outer surface which is substantially aligned with the sidewall surface of the opening.

FIGS. 2C and 2D are cross-sectional views of the semiconductor structure 200A after performing operation 105. In FIG. 2C, a first electrode material 213 is overfilled in the opening 211 in the memory region 201. The first electrode material 213 also forms over a top surface 209A of the protection material 209 in the memory region 201 and in the periphery region 202. Possible formation methods include electroless plating, sputtering, electro plating, PVD or ALD. The first electrode material 213 includes a conductive material having a proper work function such that a high work function wall is built between a subsequently formed first electrode and a resistance variable layer. The first electrode material 213 may comprise Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, Cu or combinations thereof. In some embodiments, the excess first electrode material 213 outside the opening 211 is removed through a suitable planarization process such as CMP to reduce a thickness of the first electrode material 213 about 30 Å to 500 Å above the top surface 209A of the protection material 209.

In FIG. 2D, the first electrode material 213 is etching back to form a first electrode 213E filled in a bottom section of the opening 209 in the memory region 201. The first electrode material 213 in the periphery region 202 is completely removed. The first electrode 213E is electrically connected to an underlying transistor through the conductive structure 205. The first electrode 213E is surrounded by the protection material 209 and the etching stop layer 207. The first electrode 213E has a top surface 213A and a first outer surface 213B. In certain embodiments, the planarization process is performed on the first electrode material 213 to create a substantially flat top surface and the etching back process reduces the thickness of the first electrode material 213 in the opening 211 to duplicate a substantially flat top surface 213A for the first electrode 213E. Due to first electrode material 213 filled in the opening 211, the first outer surface 213B of the first electrode 213E is substantially aligned with the interior sidewall surface 211A of the opening 211.

Referring back to FIG. 1, method 100 continues with operation 106. In operation 106, a resistance variable layer is deposited in the opening over the first electrode. The resistance variable layer has a first portion and a second portion. The first portion is over the top surface of the first electrode. The second portion extends upwardly from the second portion and has a second outer surface substantially aligned with the sidewall surface of the opening.

FIG. 2E is a cross-sectional view of the semiconductor structure 200A after performing operation 106. In some embodiments, a resistance variable layer 215 is conformally deposited over the top surface 209A of the protection material 209 and along the interior sidewall surface 211A of the opening 211, and over the top surface 213A of the first electrode 213. After the formation of the resistance variable layer 215, the opening 211 partially filled with the resistance variable layer 215 becomes a remaining opening 216. The resistance variable layer 215 has a resistivity capable of switching between a high resistance state and a low resistance state (or conductive), by application of an electrical voltage. In various embodiments, the resistance variable layer 215 includes at least one of dielectric materials comprising a high-k dielectric material, a binary metal oxide and a transition metal oxide. In some embodiments, the resistance variable layer 215 includes nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, zinc oxide, tungsten oxide, aluminum oxide, tantalum oxide, molybdenum oxide or copper oxide. Possible formation methods include pulse laser deposition (PLD) or ALD, such as ALD with a precursor containing zirconium and oxygen. In one example, the resistance variable layer 215 has a thickness in a range from about 10 Å about 500 Å.

Referring back to FIG. 1, method 100 continues with operation 107. In operation 107, a second electrode material is formed over the resistance variable layer.

FIG. 2F is a cross-sectional view of the semiconductor structure 200A after performing operation 107. A second electrode material 217 is deposited over the resistance variable layer 215 and overfills the opening 216. The second electrode material 217 may include suitable conductive materials to electrically connect a subsequently formed resistance variable memory structure to other portions of an interconnect structure for electrical routing. The second electrode material 217 may comprise Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, Cu or combinations thereof. In at least one example, the second electrode material 217 has a thickness above a top surface 215A of the resistance variable layer 215 in a range from about 30 Å about 3000 Å. In some embodiments, the first electrode material 213 and the second electrode material 217 have a same composition. In some embodiments, the first electrode material 213 and the second electrode material 217 have different compositions. Possible formation methods for the second electrode material 217 include electroless plating, sputtering, electro plating, PVD or ALD.

Referring back to FIG. 1, method 100 continues with operation 108. In operation 108, the second electrode material and the resistance variable layer is patterned to form a second electrode over the first electrode.

FIG. 2G is a cross-sectional view of the semiconductor structure 200A after performing operation 108. A resistance variable memory structure 230 is formed in the memory region 201 by suitable patterning processes, including lithography patterning, and etching processes. The etching stop layer 207 may cease the etching processes further go down to the dielectric layers 203 and the conductive structure 205 during a formation stage for a second electrode (217A and 217H). In the periphery region 201, all the layers above the etching stop layer 207 are removed.

The resistance variable memory structure 230 includes the first electrode 213E, a resistance variable layer 215A-C, a protection material 209 and the second electrode (217V and 217H). The first electrode 213E is surrounded by the etching stop layer 207 and the protection material 209. The resistance variable layer 215A-C has a first portion 215A, a second portion 215B and a third portion 215C. The first portion 215A is disposed over the top surface 213A of the first electrode 213E. The second portion 215B extends upwardly from the first portion 215A. The third portion 215C extends horizontally away from the second portion 215B, beyond an edge of the first electrode 213E, and overlies the top surface 209A of the protection material 209. The second electrode (217V and 217H) comprises a vertical portion 217V and a horizontal portion 217H. The vertical portion 217V extends into an opening surrounded by the second portion 215B of the resistance variable layer. The horizontal portion 217H extends beyond the second outer sidewall surface 211B of the second portion 215B of the resistance variable layer. The protection material 209 has the interior sidewall surface 211A and an outer sidewall surface 209B. The interior sidewall surface 211A of the protection material 209 is substantially aligned with the first outer sidewall surface 213B of the first electrode 213E and the second outer sidewall surface 211B of the second portion 215B of the resistance variable layer. The outer sidewall surface 209B of the protection material 209 is substantially aligned with edges of the third portion 215C of the resistance variable layer and substantially aligned with edges of horizontal portion 217H of the second electrode.

Referring back to FIG. 1, the method 100 optionally continues with operation 109 in which a conductive plug is formed contacting the second electrode.

FIG. 2H is a cross-sectional view of the semiconductor structure 200A after performing operation 109. An inter-level dielectric (ILD) layer 219 may be blanket formed over the memory region 201 and the periphery region 202 shown in FIG. 2G. A chemical mechanical polishing (CMP) process is further applied to the semiconductor structure 200A to planarize the ILD layer 219. The ILD layer 219 may include multiple dielectric layers. The ILD layer 219 may comprise silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, tetra-ethyl-ortho-silicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, spin-on glass (SOG), low-k dielectric material, or combinations thereof.

In certain embodiments, a dual damascene process is performed in the ILD layer 219 to form conductive wires 223A-B and contact plugs 221A-B in the memory region 201 and the periphery region 202. The conductive wires 223A-B in the memory region 201 and the periphery region 202 are in a same second metal line layer above an underlying first metal line layer. In the memory region 201, the resistance variable memory structure 230 is interposed between the first metal line layer and the second metal line layer. The contact plugs 221A contacts the horizontal portion 217H of the second electrode and connects to the conductive wires 223A in the second metal line layer. In the periphery region 202, none device structure is interposed between the first metal line layer and the second metal line layer. The device structure includes diode, transistor, PN junction, resistor, capacitor or inductor. The contact plug 221B connects the conductive wires 223B in the second metal line layer and the conductive structure 205. In some embodiments, the conductive structure 205 is a conductive wire in the first metal line layer. In certain embodiments, the conductive structure 205 is a contact plug above a conductive wire in the first metal line layer. A conductive material of the conductive wires 223A-B and contact plugs 221A-B includes copper, copper alloys, aluminum or tungsten.

Advantageously, the resistance variable memory structure 230 may be formed using, at least in part, some of the same process steps that simultaneously form desire structures in the periphery region 202 (or logic region) of the semiconductor structure 200A. The manufacturing complexity and cost are reduced in accordance with some embodiments.

FIG. 2H also illustrates the resistance variable memory structure 230 in various operations for data storage. In a “forming” operation, a “forming” voltage is applied to the first and second electrodes 213E and 217H, respectively. The “forming” voltage is high enough to generate a conductive portion in the first portion 215A of the resistance variable layer. In one example, the conductive portion includes one or more conductive filaments 250 to provide a conductive path such that the first portion 215A of the resistance variable layer shows an “on” or low resistance state. The conductive path may be related to the lineup of the defect (e.g. oxygen) vacancies in the first portion 215A of the resistance variable layer. In some embodiments, the “forming” voltage is applied only one time. Once the conductive path is formed, the conductive path will remain present in the resistance variable layer 215A. Other operations (reset operation and set operation) may disconnect or reconnect the conductive path using smaller voltages or different voltages.

Advantageously, the protection material 209 includes a substantially oxygen-free dielectric material. The protection material 209 surrounds the first portion 215A and second portion 215B of the resistance variable layer, and a top portion of the first electrode 213E. The protection material 209 may prevent the lineup of the defect (e.g. oxygen) vacancies for conductive paths 250 in the second portion 215B disturbed by oxygen atoms from adjacent layers. The electrical characteristic stability and reliability for the resistance variable memory structure 200A is enhanced.

FIGS. 2I to 2J are certain embodiments of a semiconductor structure 200B having a resistance variable memory structure at various stages of manufacture of the method 100 of FIG. 1. Some of the structures in FIGS. 2I to 2J may be substantially similar to the embodiments disclosed in FIGS. 2A to 2F and the description of the common structures are not repeated here although fully applicable in the following embodiments as well.

Referring to FIG. 2I, which is a cross-sectional view of a semiconductor structure 200B continued after the process operation in FIG. 2F. Details of the materials and fabrication methods of the semiconductor structure 200B before FIG. 2I can be found in the text associated with the semiconductor structure 200A in FIGS. 2A-2F and are not repeated here.

In FIG. 2I, a planarization process such as CMP is performed to remove the excess second electrode material 217 and the resistance variable layer 215 outside the opening 211 in FIG. 2F. The second electrode material 217 and the resistance variable layer 215 are patterned within the opening 211 through the planarization process to form a second electrode 217E over the first electrode 213E. Thus, a resistance variable memory structure 230 is formed.

The resistance variable memory structure 230 includes the first electrode 213E, a resistance variable layer 215A-B, a protection material 209 and the second electrode 217E. The first electrode 213E is surrounded by the etching stop layer 207 and the protection material 209. The resistance variable layer 215A-B has a first portion 215A and a second portion 215B. The first portion 215A is disposed over the top surface 213A of the first electrode 213E. The second portion 215B extends upwardly from the first portion 215A. The second electrode 217E is surrounded by the second portion 215B of the resistance variable layer. The protection material 209 has the interior sidewall surface 211A adjacent to the first outer sidewall surface 213B of the first electrode 213E and the second outer sidewall surface 211B of the second portion 215B of the resistance variable layer. The second electrode 217E, the second portion 215B of the resistance variable layer and the protection material 209 have a same substantially flat top surface 209A. The protection material 209 surrounds the first portion 215A and second portion 215B of the resistance variable layer, and a top portion of the first electrode 213E. The protection material 209 may prevent the lineup of the defect (e.g. oxygen) vacancies for conductive paths 250 in the second portion 215B disturbed by oxygen atoms from adjacent layers.

FIG. 2J is a cross-sectional view of the semiconductor structure 200B after forming an ILD layer 219 over top surface 209A of the protection material 209 and forming conductive wires 223A-B and contact plugs 221A-B in the memory region 201 and the periphery region 202. Details of the materials and fabrication methods of the semiconductor structure 200B in FIG. 2J can be found in the text associated with the semiconductor structure 200A in FIG. 2H and are not repeated here.

The conductive wires 223A-B in in the memory region 201 and the periphery region 202 are in a same second metal line layer above an underlying first metal line layer. In the memory region 201, the resistance variable memory structure 230 is interposed between the first metal line layer and the second metal line layer. The contact plugs 221A contacts the second electrode E and connects to the conductive wires 223A in the second metal line layer. In the periphery region 202, none device structure is interposed between the first metal line layer and the second metal line layer. The device structure includes diode, transistor, PN junction, resistor, capacitor or inductor. The contact plug 221B connects the conductive wires 223B in the second metal line layer and the conductive structure 205. In some embodiments, the conductive structure 205 is a conductive wire in the first metal line layer. In certain embodiments, the conductive structure 205 is a contact plug above a conductive wire in the first metal line layer.

FIGS. 2K to 2L are some embodiments of a semiconductor structure 200C having a resistance variable memory structure at various stages of manufacture of the method 100 of FIG. 1. Referring to FIG. 2K, which is a cross-sectional view of a semiconductor structure 200C continued after the process operation in FIG. 2I. Details of the materials and fabrication methods of the semiconductor structure 200C before FIG. 2K can be found in the text associated with the semiconductor structure 200B in FIGS. 2A-2F and FIG. 2I. The description is not repeated here.

In FIG. 2K, a resistance variable memory structure 230 is formed in the memory region 201 by performing suitable patterning processes on the semiconductor structure 200B shown in FIG. 2I. The suitable patterning processes include lithography patterning and etching processes. The etching stop layer 207 may cease the etching processes further go down to the dielectric layers 203 and the conductive structure 205. In the periphery region 201, all the layers above the etching stop layer 207 are removed.

The resistance variable memory structure 230 includes the first electrode 213E, a resistance variable layer 215A-B, a protection material 209 and the second electrode 217E. The first electrode 213E is surrounded by the etching stop layer 207 and the protection material 209. The resistance variable layer 215A-B has a first portion 215A and a second portion 215B. The first portion 215A is disposed over the top surface 213A of the first electrode 213E. The second portion 215B extends upwardly from the first portion 215A. The second electrode 217E is surrounded by the second portion 215B of the resistance variable layer. The protection material 209 has the interior sidewall surface 211A and an outer sidewall surface 209B. The interior sidewall surface 211A is adjacent to the first outer sidewall surface 213B of the first electrode 213E and the second outer sidewall surface 211B of the second portion 215B of the resistance variable layer. The outer sidewall surface 209B is substantially parallel to the interior sidewall surface 211A. The second electrode 217E, the second portion 215B of the resistance variable layer and the protection material 209 have a same substantially flat top surface 209A. The protection material 209 surrounds the first portion 215A and second portion 215B of the resistance variable layer, and a top portion of the first electrode 213E. The protection material 209 may prevent the lineup of the defect (e.g. oxygen) vacancies for conductive paths 250 in the second portion 215B disturbed by oxygen atoms from adjacent layers.

FIG. 2L is a cross-sectional view of the semiconductor structure 200C after forming an ILD layer 219 over top surface 209A of the protection material 209 and forming conductive wires 223A-B and contact plugs 221A-B in the memory region 201 and the periphery region 202. Details of the materials and fabrication methods of the semiconductor structure 200C in FIG. 2K can be found in the text associated with the semiconductor structure 200A in FIG. 2H and are not repeated here.

The conductive wires 223A-B in the memory region 201 and the periphery region 202 are in a same second metal line layer above an underlying first metal line layer. In the memory region 201, the resistance variable memory structure 230 is interposed between the first metal line layer and the second metal line layer. The contact plugs 221A contacts the second electrode E and connects to the conductive wires 223A in the second metal line layer. In the periphery region 202, none device structure is interposed between the first metal line layer and the second metal line layer. The contact plug 221B connects the conductive wires 223B in the second metal line layer and the conductive structure 205.

One aspect of the disclosure describes a semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer.

A further aspect of the disclosure describes a semiconductor structure including a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer and a second electrode. The first electrode has a top surface and a first outer sidewall surface. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode. The second portion extends upwardly from the first portion and has a second outer sidewall surface substantially aligned the first outer sidewall surface of the first electrode. The second electrode is disposed over the resistance variable layer.

The present disclosure also describes an aspect of a method of forming a resistance variable memory structure. The method includes forming a protection material over a conductive structure. An opening is etched in the protection material to expose a portion of the conductive structure. The opening has a sidewall surface. The opening is partially filled with a first electrode material over the conductive structure to form a first electrode. The first electrode has a top surface and a first outer surface substantially aligned with the sidewall surface of the opening. A resistance variable layer is deposited in the opening over the first electrode. The resistance variable layer has a first portion and a second portion. The first portion is over the top surface of the first electrode. The second portion extends upwardly from the first portion and has a second outer surface substantially aligned with sidewall surface of the opening. A second electrode material is formed over the resistance variable layer. The second electrode material and the resistance variable layer are patterned to form a second electrode over the first electrode.

Although the embodiments and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

What is claimed:
 1. A method of forming a semiconductor device, comprising: forming a protection material over a conductive structure disposed on a substrate, wherein the protection material is formed in a memory region and a periphery region of the substrate; etching an opening in the protection material exposing a top surface of the conductive structure in the memory region; depositing a first conductive material in the opening; etching back the deposited first conductive material such that a top surface of the deposited first conductive material in the opening is lower than a top surface of the protection material; forming a resistance variable layer and a second conductive material in the opening on the etched back first conductive material; forming a memory structure by patterning the second conductive material, the resistance variable layer and the protective layer such that a sidewall of each of the second conductive material, the resistance variable layer and the protective layer are coplanar; depositing a dielectric layer over the memory structure and the periphery region of the substrate; and forming a first contact plug in the dielectric layer interfacing with the memory structure and a second, coplanar, contact plug in the dielectric layer of the periphery region of the substrate.
 2. The method of claim 1, wherein the patterning the protective layer includes removing the protective layer from the periphery region of the substrate.
 3. The method of claim 1, wherein the depositing the first conductive material in the opening includes depositing the first conductive material over the memory region and the periphery region, wherein after the depositing the first conductive material, a planarization process is performed on the first conductive material prior to the etching back the first conductive material.
 4. The method of claim 1, wherein the patterning the second conductive material, the resistance variable layer and the protective layer removes each of the second conductive material, the resistance variable layer and the protective layer from the periphery region on the substrate.
 5. The method of claim 1, further comprising: depositing an etch stop layer under the protection material and over the substrate.
 6. The method of claim 5, wherein the patterning the second conductive material, the resistance variable layer and the protective layer includes etching the second conductive material, the resistance variable layer and the protective layer, wherein the etching stops at the etch stop layer.
 7. The method of claim 5, wherein the depositing the etch stop layer includes depositing a conformal layer extending from the memory region to the periphery region of the substrate.
 8. The method of claim 7, wherein the forming the dielectric layer includes depositing the dielectric layer on the etch stop layer in the periphery region.
 9. The method of claim 1, further comprising: planarizing the deposited dielectric layer before forming the first contact plug and the second contact plug.
 10. The method of claim 1, wherein the first contact plug has a first length and the second contact plug has a second length, the second length being greater than the first length.
 11. A method of forming a semiconductor device, comprising: forming a protection material over a conductive structure disposed on a substrate, wherein the protection material is formed in a memory region and a periphery region of the substrate; etching an opening in the protection material exposing a top surface of the conductive structure in the memory region; forming a first electrode, a resistance variable layer, and a second electrode material in the opening; planarizing the resistance variable layer, the second electrode material and the protection material, wherein the planarizing includes planarizing the protection material in the periphery region; forming a dielectric layer on the memory region and the periphery region, wherein the dielectric layer is formed on the planarized resistance variable layer, planarized second electrode material and the planarized protection material in the memory region; and forming a first contact plug in the dielectric layer interfacing with the planarized second electrode material and forming a second, coplanar, contact plug in the dielectric layer of the periphery region of the substrate.
 12. The method of claim 11, wherein the forming the dielectric layer includes depositing the dielectric layer over the planarized protection layer in the periphery region.
 13. The method of claim 11, wherein the forming the dielectric layer includes depositing the dielectric layer directly on a top surface of the planarized protection layer in the periphery region.
 14. The method of claim 11, wherein the forming the protection material includes depositing a substantially oxygen free material.
 15. The method of claim 11, wherein the planarizing the resistance variable layer and the second electrode material includes removing the resistance variable layer and the second electrode material from the periphery region of the substrate.
 16. The method of claim 11, further comprising: after planarizing the resistance variable layer, the second electrode material and the protection material, patterning the protection material including removing the protection material from the periphery region of the substrate.
 17. A method of forming a semiconductor device, comprising: forming a protection material over a substrate, wherein the protection material is formed in a memory region and a periphery region of the substrate; etching an opening in the protection material in the memory region; depositing a first conductive material, a resistance variable layer, and a second conductive material in the opening; providing a memory structure including the first conductive material, the resistance variable layer, and the second conductive material in the memory region while removing the first conductive material and the resistance variable layer from the periphery region, wherein the protection material is disposed on sidewalls of the memory structure; depositing a blanket layer of dielectric material over the memory structure and the periphery region of the substrate; planarizing the deposited blanket layer of dielectric material; and forming a first contact plug and second contact plug in the planarized dielectric material, wherein the first contact plug interfaces the memory structure.
 18. The method of claim 17, further comprising: forming an etch stop layer over the substrate under the protection material, wherein the etch stop layer is disposed on the memory region and the periphery region of the substrate.
 19. The method of claim 17, wherein the forming the first and second contact plugs includes a dual damascene process.
 20. The method of claim 17, further comprising: depositing a conductive wire over and interconnected with the first contact plug and the second contact plug. 